REDUCE AREA AND LEAKAGE POWER BY USING GDI TECHNIQUE AND HIGH Vth TRANSISTOR

Abstract

High device density and low threshold voltages resulted rapid increase in leakage power dissipation. Reduction of leakage power in CMOS VLSI has been the research interest for the several years. In CMOS IC design there is an important tradeoff between technology scaling and static power consumption .In today’s technology leakage power play a significant role. As we approaching to nanoscale design the total chip power consumption becomes dependent on leakage power. Many techniques had been proposed to tackle the problem. In this paper, new method has been proposed for reducing leakage power in 90nm technology. The simulation tool used is Tanner EDA.

Keywords – Power dissipation, leakage power, power gating, GDI Technique.